(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for integrating dynamic random access memory (DRAM) circuits with logic circuits. The method is particularly useful for integrating DRAM cells with field effect transistors (FETs) formed by the self-aligned silicide (SALICIDE) process. The DRAM process is compatible with the salicide process by reducing the thermal budget (time at temperature) required for processing the merged logic/DRAM chips. The method uses two levels of metal to concurrently form the DRAM capacitors and the metal interconnections for the logic, thereby providing a plane structure using a cost-effective process.
(2) Description of the Prior Art
Merged logic and memory circuits are finding extensive use in the electronics industry. These circuits, such as microprocessors, are used in the computer industry for general purpose computing. Merged integrated circuits are also used for application-specific circuits (ASC) in other industries, such as automobiles, toys, communications, the like.
To optimize these merged circuits, it is desirable in the electronics industry to fabricate the FETs for the logic and DRAM circuits having different processes and therefore different electrical parameters. For example, it is desirable to use a thin gate oxide for the logic FETs and the peripheral circuits for the DRAM FETs to increase performance (circuit speed), while it is desirable to use a thicker gate oxide, narrower sidewall spacers, and self-aligned contacts (SACs) for the FET access transistors of the DRAM memory cells because of the higher gate voltage (V.sub.g), and also to achieve high density of memory cells and higher yield. It is desirable to integrate the logic and memory circuits on the same chip using shared process steps to minimize the manufacturing costs.
The process of choice for making the FETs for the logic circuits on the chip is to use the self-aligned silicide process (SALICIDE process) and to use tungsten silicide FET gate electrodes for the memory cell region. The SALICIDE process for the logic consists of forming a doped electrically conducting polysilicon layer which is patterned to form the FET gate electrodes over a thin gate oxide on the silicon substrate. Lightly doped drain (LDD) areas are formed adjacent to the gate-electrode regions, and insulating sidewall spacers are formed on the gate electrodes. A second implant is used to form the ohmic source/drain contacts in the substrate adjacent to the sidewalls. A thin metal layer, such as titanium (Ti), is deposited and annealed to form a TiSi.sub.X on the exposed silicon surfaces of the gate electrodes and on the adjacent source/drain contact areas. The unreacted Ti on the insulating surfaces (e.g., silicon oxide) is selectively removed to complete the SALICIDE FETs.
When the channel length of the FET is reduced (currently to less than 0.18 micrometers) to improve circuit performance, it is necessary to use very shallow diffused junctions for the implanted source/drain areas and thin metal silicide contacts to avoid short channel effects, such as punchthrough, Unfortunately, in the current DRAM circuit of choice, the memory cells are fabricated using stacked capacitors which are formed over the memory cell areas after the SALICIDE FETs are completed. The conventional DRAM capacitors are formed using several layers of doped poly-silicon which require high-temperature processing for extended periods of time that can electrically degrade the very shallow (&lt;0.1 um) implanted source/drain junctions and the thin TiSi.sub.X contacts. Therefore, there is a strong need in the industry to fabricate DRAM stacked capacitors at reduced temperatures and/or shortened times (commonly referred to as the "thermal budget" in the industry) to prevent degrading the narrow channel/shallow junction FET devices.
Numerous methods of forming logic circuits with embedded DRAM devices have been reported in the literature. One method of making merged or embedded DRAM devices with logic circuits is described in U.S. Pat. No. 5,858,831 to Sung. Sung's method teaches a process for forming FETs for logic and for DRAMs having different gate oxide thicknesses, while minimizing the number of masking steps. Huang in U.S. Pat. No. 5,863,820 teaches a method for integrating DRAMs with self-aligned contacts and salicide FETs for logic on the same chip. Yoo et al. in U.S. Pat. No. 5,719,079 describe a method for making static RAM (SRAM) using a salicide process. However, none of the references addresses making low-temperature DRAMs embedded with logic circuits having salicide FETs.
Therefore there is still a need in the semiconductor industry to fabricate embedded DRAM devices using a low thermal budge process to prevent electrical degradation of the salicide PETs while providing a cost-effective manufacturing process.